A Semi-Canonical Form for Sequential AIGs

Dr Alan Mishchenko from UC Berkeley visited our group in January, 2013

Abstract
In numerous EDA flows, time-consuming computations are repeatedly applied to sequential circuits. This calls for methods to determine what circuits have been processed already by a tool. This talk proposes an algorithm for semi-canonical labeling of nodes in a sequential AIG, allowing problems or sub-problems solved by an EDA tool to be cached. This can result in a speedup when the tool is applied to designs with isomorphic components or design suites exhibiting substantial structural similarity.

Biography
Alan Mishchenko graduated from Moscow Institute of Physics and Technology (Moscow, Russia) in 1993 with M.S.and received his Ph.D. from the Glushkov Institute of Cybernetics (Kiev, Ukraine) in 1997. From 1998 to 2002 he was an Intel-sponsored visiting scientist at Portland State University. In 2002, he joined the EECS Department at UC Berkeley, where he is currently an associate researcher in the group of Professor Brayton. Alan's research interests are in developing computationally efficient methods for synthesis and verification.