A field-programmable gate array for floating-point computation

Prof. Wayne Luk from Imperial College London visited our group in November, 2011

Abstract
This talk presents a field-programmable gate array (FPGA) optimised for floating-point computation. In this architecture, fine-grained units are used for implementing control logic and bit-oriented operations, while reconfigurable word-based coarse-grained units incorporating word-oriented lookup tables and floating-point operations are used to implement datapaths. A method involving the adoption of existing FPGA resources to model the size, position and delay of the proposed reconfigurable architecture has been developed. On selected floating-point benchmark circuits, the proposed architecture is estimated to offer 4 times improvement in speed, 25 times reduction in area, and 14 times reduction in energy consumption relative to a commercial FPGA device in comparable technology.

Biography
Dr Wayne Luk is Professor of Computer Engineering at Imperial College London. He founded and leads the Computer Systems Section and the Custom Computing Group in Department of Computing, and was Visiting Professor at Stanford University and Queen's University Belfast. His research interests include reconfigurable computing, field-programmable technology, and design automation. He developed hardware compilation techniques based on syntax-directed translation, pipeline vectorization, and source-level transformation; he contributed to optimizations for run-time reconfiguration, custom instruction processors, and programmable embedded-block architecture for field-programmable devices. He received many awards at international conferences, including FPL (2004, 2007, 2008, 2010), ERSA (2004), FPT (2005, 2008), ASAP (2008), SAMOS (2008), and SPL (2008, 2009). He led a team winning two Platform Grants from UK Engineering and Physical Sciences Research Council, and a Research Excellence Award from Imperial College.  He is a Fellow of the IEEE and a Fellow of the BCS, and is Editor-in-Chief for ACM Transactions on Reconfigurable Technology and Systems. He received his MA, MSc and DPhil degrees from University of Oxford.